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Additional info for ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings)

Example text

Starting with a trivial tree containing only the source pin, we incrementally add one edge at a time to the growing tree. At each step we compute the maximum delay from the source to any sink in the tree. 665 SPICE delay ratios of all 125 topologies for IN} = 5 using ICM technology parameters. All values are normalized to the delay value for the best topology, and are averaged over 20 random sets of pin locations. Table 4: Branch-and- Bound Optimal Routing Tree (BBORT) Method Input: signal net N with source no E N Output: optimal-delay tree T 0pt over N (9) 1.

So the time complexity is that of the group formation phase (N * 4/3). TSPMS (TPMS){ for (each realisation r in r) { I Find a realisation R in ' so that their corresponding D is minimised; for Let ml and M2 be the number of combinations Merge r and R to form a realisation of M, U M,; the 1, each side of the PMS: According to definition number of realisations created by Realise-SPMS is for (each realisation R in ') { equal to: Find a realisation r in r so that their N2 N. corresponding D is minimised; (2) + I k(j) o O(koP) ml + m 2 =lk(i) Merge R and r to form a realisation of M, U Mt; Return (Q); 1=1 j=1 } where o, is the order of SPMSs.

According to equation 2, the number of realizations of iF increases as O(k ). The order of the complexity of the number of the realisations that need to be investigated (O(F)) is a key point in the area optimisation problem. The bipartite graph is used in our representation and an optimal algorithm is used to minimise the order. 2 and P is the number of SPMSs. Since the SRT is optimal, W is minimised. As the order of SPMS is usually smaller than W, equation 3 becomes: O(F) oc O(T * kW) (4) For a given flooplan topology, its W is intrinsic and measures the scale of the complexity of the problem when it is realised.

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